Some buck converters have a light-load mode, known as PFM or gated oscillator mode. (In this invention disclosure, this mode is called as ‘sleep’). In this sleep mode, the buck converter stops switching for a while until output voltage hits the defined lower threshold voltage. Especially in portable buck converter applications, most of circuits are disabled during this sleep mode to reduce the current consumption and to improve the efficiency at light load. Major challenge of this mode is transient response. When the output load changes from light load to heavy load, the converter has to change the operation mode from sleep to normal switching mode (PWM/Sync), because sleep mode cannot stably handle high output load. However, the error amplifier is usually disabled during sleep mode and it takes time to wake up. Especially, it is very difficult to set a proper compensation capacitor voltage in the error amplifier instantly. Improper voltage of compensation capacitor leads to significant output voltage disturbance when the PWM control loop takes over the buck converter control.
One solution of above problem is to hold the compensation capacitor voltage in the sleep mode, i.e. setting capacitor output as high impedance and let the capacitor keep the previous voltage in PWM mode. By this, when the converter goes back to PWM mode from sleep, the error amplifier can start-up in proper output voltage and smooth mode change can be achieved.
However, there are two critical issue of this. One is leak current. In practice in semiconductor circuits, even when a transistor is off, there are some leak currents. If the sleep mode continues for a long-time, then the capacitor voltage will be discharged by such a leak current and cannot hold appropriate voltage. Another issue is input voltage change. If the input voltage changes significantly during sleep mode, appropriate duty cycle, error amplifier voltage, and compensation capacitor voltage will be changed. In this case, even if the compensation capacitor keeps the previous voltage, that is not an appropriate voltage, so the output voltage disturbance will occur at mode change.
It is a challenge to designers of DC-to-DC converters as buck converters, boost converters, or buck/boost converters to overcome the disadvantages mentioned above.